`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	ls_wb_u(
    input				clk,
    input				rst_n,
    input               flush,
    input				ena,

    input           WB_sel_lsu,
    output		    WB_sel_wbu,
    
    input            Reg_W_lsu,
    output           Reg_W_wbu,

    input	[63:0]		Rd_lsu,
    output  [63:0]      Rd_wbu,

    input   [63:0]    Load_data_lsu,
    output  [63:0]    Load_data_wbu,

    input   [4: 0]      rd_lsu,
    output  [4: 0]      rd_wbu
);
    pip_reg  #(.N(5),.zero(5'd0))
        u_rd_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i     (rd_lsu),
                .data_o     (rd_wbu)
            );

    pip_reg  #(.N(64),.zero(64'd0))
            u_RD_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (Rd_lsu),
                    .data_o  (Rd_wbu)
                );

    pip_reg  #(.N(64),.zero(64'd0))
            u_LD_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (Load_data_lsu),
                    .data_o  (Load_data_wbu)
                );

    pip_reg  #(.N(2),.zero(2'b0))
        u_ctrl_sel_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i   ({WB_sel_lsu,Reg_W_lsu}),
                .data_o   ({WB_sel_wbu,Reg_W_wbu})
            );

    
endmodule